Along with the advancement in the fabrication process of integrated circuit (IC), the surface areas of ICs have been greatly reduced. Accordingly, the fabricating costs of ICs are reduced and the performances thereof are improved. However, the power consumption per unit area of a system on chip (SoC) may be greatly increased due to the increase in leakage current and operating frequency. The increase in the power consumption will affect the stability and lifespan of the device. Thus, power consumption has become one of the key factors for determining the quality of a battery-powered portable product.
In a SoC, a static random access memory (SRAM) takes up a great portion of the circuit area and is a volatile memory with high access speed. When the SoC enters a sleep mode, in order to keep the data in the SRAM, the power supplied to the SRAM cannot be cut off. Herein considerable power is unnecessarily consumed due to leakage current, and this situation deteriorates along with the increase in the capacity of the SRAM and the process shrink. Contrarily, if a non-volatile memory (NVM) is adopted, the power supplied to the NVM can be cut off in the sleep mode so that no power will be consumed. However, none of existing NVMs in mass production or development can achieve the operation speed of a SRAM.
Thereby, if a SRAM and a NVM can be combined, the original characteristic of the SRAM can be kept and the power consumed due to leakage current in the sleep mode can be avoided by cutting off the power supply.